CPU Caches are powerful sources of information leakage. To develop practical Cache-based attacks, the need for automation of the process of finding exploitable Cachebased side-channels in computer systems is felt more than ever. Cache template attack is a generic technique that utilizes Flush+Reload attack in order to automatically exploit Cache vulnerability of Intel platforms. Cache template attack on the T-table-based AES implementation consists of two phases including the pro, ling phase and key exploitation phase. Pro, ling is a preprocessing phase to monitor dependencies between the secret key and behavior of the Cache memory. In addition, the addresses of T-tables can be obtained automatically. At the key exploitation phase, Most Significant Bits (MSBs) of the secret key bytes are retrieved by monitoring the exploitable addresses. This study proposed a simple yet effective searching technique, which accelerates the pro, ling phase by a factor of utmost 64. In order to verify the theoretical model of our technique, the mentioned attack on AES was implemented. The experimental results revealed that the pro, ling phase runtime of the Cache template attack was approximately 10 minutes, while the proposed method could speed up the running of this phase up to almost 9 seconds.

With the development of the electronic industry and the advent of modern processors, the attack model in the algorithms and encryption protocols also changed. In spite of computational complexity in algorithms and cryptographic protocols, implementations can be a factor for the leakage of confidential information. The attacker can attack when electronic components are executing the encryption operators using the secret key on sensitive data. As a result of computing, there is a leak of information in electronic components where attacks are called side-channel attacks. one of the most important sources of information leakage of side channels is time changes due to the execution of computation. The accesses to memory and the presence of branches in the program are expensive at runtime, so the processors use Cache memory and branch-prediction to reduce this cost. Unfortunately, this optimization during execution leads to time changes in the execution of a program. The Cache in the time side-channel attacks is more challenging and more practical. In this paper, we will review a variety of memory attacks on the implementation of the AES cipher algorithm. by implementing the attacks and comparing the results, we will extract and compare the security weaknesses of implementing the AES cipher algorithm against Cache attacks.

Distributed Denial of Service (DDoS) attacks are among the primary concerns in internet security today. Machine learning can be exploited to detect such attacks. In this paper, a multi-layer perceptron model is proposed and implemented using deep machine learning to distinguish between malicious and normal traffic based on their behavioral patterns. The proposed model is trained and tested using the CICDDoS2019 dataset. To remove irrelevant and redundant data from the dataset and increase learning accuracy, feature selection is used to select and extract the most effective features that allow us to detect these attacks. Moreover, we use the grid search algorithm to acquire optimum values of the model’s hyperparameters among the parameters’ space. In addition, the sensitivity of accuracy of the model to variations of an input parameter is analyzed. Finally, the effectiveness of the presented model is validated in comparison with some state-of-the-art works.

An important category of the side-channel attacks takes advantage of the fact that Cache leads to temporal changes in the execution of encryption algorithms and thus information leakage. Although side-channel attacks based on high Cache memory are among the most widely used side-channel attacks, they have been less studied than other side-channel attacks. Accordingly, extensive research has been conducted by the cryptographic community in the area of side-channel attacks based on Cache memory. The focus of research has mainly been on the security of encryption algorithms implemented by Intel and Pentium processors, which due to the different Cache structure of different processors, cannot be extended to other commonly used processors such as ARM. In response to this challenge, new research is focusing on Cache-based side-channel attacks on various mobile processors and other applications including ARM processors. The different Cache structure and lack of support for some of the commands needed to execute Cache attacks have made it difficult to execute these attacks on ARM processors. In this paper, we first investigate the Cache-timing attack using a collision event on one of the ARM processors. In this attack, the attacker only needs to measure the timing of the encryption, and unlike the access-driven attacks, the attacker does not need access to the victim's Cache. We also implemented the attack using an industrial automation board called Raspberrypi3, which runs the router operating system, the results of which show the accuracy of the attack.

The template attack is one of the most e cient attacks for exploiting the secret key. template-based attack extracts a model for the behavior of side channel information from a device that is similar to the target device and then uses this model to retrieve the correct key on the target victim device. Until now, many researchers have focused on improving the performance of template attacks, but recently, a few countermeasures have been proposed to protect the design against these attacks. On the other hand, researches show that regular countermeasures against these attacks are costly. Randomized shu ing in the time domain is known as a cost-e ective countermeasure against side-channel attacks that are widely used. In this article, we implemented an actual template attack and proposed an e cient countermeasure against it. We focus on the time shifting method against template attack. The results show that template attack is very susceptible to this method. The performance of attack on an AES algorithm is considerably reduced with this method. We reported the analysis results of our countermeasure. The performance of the attack can be determined according to various criteria. One of these criteria is the success rate of the attack. According to these results, template attack will be hardened signi cantly after the proposed protection such that the grade of the key recovery increases from 1 with 350K traces in unprotected design to 2 100 with 700K traces in the protected circuit. This security improvement gains in the cost of about 7% delay overhead.

Access-driven attacks are a series of Cache-based attacks using fewer measurement samples to extract sensitive key values due to the ability of the attacker to evict or access Cache lines compared to the other attacks based on this feature. Knowledge of address offset for the corresponding data blocks in cryptographic libraries is a prerequisite for an adversary to reload or evict Cache lines in Intel processors. Preventing the access of attackers to the address offsets can potentially be a countermeasure to mitigate access-driven attacks. In this paper, we demonstrate how to perform the Evict+Time attack on Intel x86 CPUs without any privilege of knowing address offsets.

Last level Cache (LLC) management can considerably improve the performance of Chip Multi Processors (CMPs) by reducing the miss rate and decreasing the average L1 miss latency. LLC management approaches try to either map data to Caches which are closer to cores, or exploit Caches of neighboring cores to increase performance and reduce off-chip misses. To reduce the miss rate, we need to use Cache slices of the other cores in NUCA architectures, but it increases the average L1 miss latency since the data to be accessed by cores are located in remote Cache slices. As a result, designing an intelligent management approach to improve the system performance on a variety of workloads and systems is necessary. In this paper, an adaptive Cache clustering called ACC is presented. ACC augments L2 Cache size by using the L2 Cache slices of neighboring cores adaptively. ACC selects Cache slices with minimum distance to the target core while evaluating the amount of L2 Cache slices being used on the surrounding tiles. To validate our approach, we apply several applications from SPEC CPU2006 and PARSEC benchmark suites. The results show the effectiveness of our approach, as we get speedup by up to 18%.

Curls and curves of a shell interweave its various strain modes and link them together. This interactional behavior has yet frustrated all attempts for the construction of shell templates, which needs for an individual element test in traditional approaches. Such a test fails to work for shell elements and must be reconstructed. In this paper, it is tried to study shell interactional behavior and strain entanglements via a microscopic investigation. This new view to the shell behavior reveals a simple method, in which shell templates are constructed by partitioning the stiffness matrix of a sample shell element into its components. Surly, sample elements have been qualified for their convergence in practice. The method is examined for axisymmetric cylindrical shell element.